Indian semiconductor ecosystem: News, Updates & Discussions.
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Qualcomm completes its 2nm tape‑out — a global milestone supported by engineering teams across India.
Are they routing the Brahmaputra water to the plant?
Thats not good.
I was of opinion that since we are establishing an industry from scratch, we might as well build a better sustainable ecosystem around it. Using desalination plants, leveraging Ocean rather than rivers and groundwater.
Well, hopefully they come around it soon. Our water management is already very poor.
DLI Scheme-Backed Chip Design Startups Continue to Attract Interest from Leading Investors
C2i Semiconductors Raises $15 Million Series A Led by Peak XV Partners - Largest Funding Round by an Indian Semiconductor Startup
C2i Designing Intelligent Power-Management Chip for Energy Efficient and Reliable High-performance Computing Systems
India’s semiconductor chip design ecosystem is steadily strengthening, with startups supported under the Design Linked Incentive (DLI) Scheme drawing growing interest from both investors and the user community. Semiconductor ventures traditionally involve long development timelines, substantial R&D investment and higher technical risk before revenues begin, often making early-stage investors cautious — and consequently, prior to 2021, venture capital investment in this sector in India remained limited.The Government of India’s DLI Scheme, announced in 2022, addresses this challenge by reducing upfront risk through financial support, access to advanced EDA tools, IP cores etc. and greater ecosystem awareness of semiconductor chip design. Startups are onboarded through a rigorous screening and evaluation process by a competent expert committee comprising technical and industry specialists, ensuring support to credible deep-tech companies. This structured intervention continues to improve investor confidence and commercial viability, leading to investors actively evaluating DLI-supported startups.
C2i Semiconductors
Incorporated in Bengaluru on 5 June 2024 by a founding team with decades of experience at global leaders such as Texas Instruments, National Semiconductor and Maxim Integrated. C2i Semiconductors was subsequently approved w.e.f. 1 November 2024 for financial support and access to advanced chip design tools under the DLI Scheme.
With semicon industry veteran Ganapathy Subramanyam, Founding Managing Partner, Yali Capital on its Board, C2i is developing power-management semiconductor solutions for next-generation AI data centres and cloud infrastructure.
With its engineering team quickly ramped up to 65 engineers, C2i has become one of the top three users amongst 100 companies of the centralized EDA tools in recent months, provided through the centralized EDA tool grid at the ChipIN Centre under the DLI Scheme.
The Challenge — Power Becomes the Limiting Factor in Modern Data Centres: As AI workloads grow modern data centres require very large and highly stable power supply. Older power systems were not designed for continuous high-density computing which leads to energy loss excess heat reliability challenges and difficulty in scaling infrastructure.
The Innovation — Rethinking Power from Grid to Core
C2i Semiconductors is redesigning how electricity flows inside a server from the incoming power source to the processor chip using a grid to core approach. Instead of improving individual components the company is developing a smart configurable power platform that automatically manages and optimizes power delivery in real time. The technology provides stable power even for heavy AI workloads, improves energy efficiency, reduces heat and failures, extends equipment life, simplifies server design, enables faster deployment and supports large scale data centre expansion.
In Simple Terms — An Intelligent Power Brain for AI Infrastructure
C2i technology works as an intelligent power control system for data centres, helping high-performance AI systems operate reliably, efficiently and continuously for next-generation digital infrastructure. C2i expects its first silicon designs to return from fabrication by mid-year, after which it plans to validate performance.Investor Confidence — Backing Deep-Tech Innovation from India
Recognising the potential of C2i’s breakthrough solution, Peak XV Partners (formerly Sequoia Capital India & SEA) has led a $15 million investment round to accelerate the development of next-generation, high-density and ultra-reliable system-level power delivery solutions. This follows a $4 million funding round led by Yali Capital in 2024, taking the cumulative investment raised to approximately ₹170 crore to date, in addition to the support received under the DLI Scheme.
Rajan Anandan, Managing Director at Peak XV, noted that C2i’s approach to power management can significantly extend GPU lifespan and unlock billions of dollars in industry savings.
Policy Alignment — Supporting India’s Design-Led Semiconductor Vision
The confidence of leading investment firm aligns with the vision articulated by Union Minister Shri Ashwini Vaishnaw that India’s semiconductor programme is built to strengthen both design and manufacturing, with a strong focus on creating domestic intellectual property and globally competitive product companies. He has emphasised that India already has a strong chip design talent base and the Government’s role is to support startups through design incentives, advance design tools, IPs and ecosystem support so that they can scale into global technology leaders and make India a trusted semiconductor partner to the world.
Not related to Indian semicon industry, but I read an interesting article today. You'll find it interesting too, I think.
Chinese scientists hit breakthrough on 2D semiconductor wafers
Quest for next-generation materials that can deliver superior performance in the coveted chips has become a global priority.
www.scmp.com
Chinese scientists had a breakthrough in growing MoS2 wafers, bringing 2d semiconductors one step closer to commercial viability.
Chinese scientists are striking a lot of gold these days. They're making breakthroughs left and right. A visible result of decades of continuous investment into their education.
Don't worry. We don't have dearth of talent either. Modi ji is doing the right thing by roping in private sector giants like Tata. Soon, we will catch up with the Chinese in semiconductor tech. Mark it.Not related to Indian semicon industry, but I read an interesting article today. You'll find it interesting too, I think.
Chinese scientists hit breakthrough on 2D semiconductor wafers
Quest for next-generation materials that can deliver superior performance in the coveted chips has become a global priority.
Chinese scientists had a breakthrough in growing MoS2 wafers, bringing 2d semiconductors one step closer to commercial viability.
Chinese scientists are striking a lot of gold these days. They're making breakthroughs left and right. A visible result of decades of continuous investment into their education.
I have chatted with a few folks who work in this industry. It's just usual China media hyping results of lab experiments. 2D materials are still far from commercial viability. No doubt this is a praise worthy scientific breakthrough. However, China isn't the first country to demonstrate this. USA is the leading by a good margin here as well..But even they won't claim 2D materials commercially viable..Not related to Indian semicon industry, but I read an interesting article today. You'll find it interesting too, I think.
Chinese scientists hit breakthrough on 2D semiconductor wafers
Quest for next-generation materials that can deliver superior performance in the coveted chips has become a global priority.
Chinese scientists had a breakthrough in growing MoS2 wafers, bringing 2d semiconductors one step closer to commercial viability.
Chinese scientists are striking a lot of gold these days. They're making breakthroughs left and right. A visible result of decades of continuous investment into their education.
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Not related to Indian semicon industry, but I read an interesting article today. You'll find it interesting too, I think.
Chinese scientists hit breakthrough on 2D semiconductor wafers
Quest for next-generation materials that can deliver superior performance in the coveted chips has become a global priority.
Chinese scientists had a breakthrough in growing MoS2 wafers, bringing 2d semiconductors one step closer to commercial viability.
Chinese scientists are striking a lot of gold these days. They're making breakthroughs left and right. A visible result of decades of continuous investment into their education.
- Lowest Recorded Contact Resistance: Led by Prof. Mayank Shrivastava, a team at IISc invented a technique to engineer graphene contacts by studying the overlap of atomic orbitals between carbon and metal atoms. This allowed them to achieve the lowest recorded resistance for a 2D material-to-metal interface.
- MXene Transistors: More recently, IISc researchers used MXenes (a class of 2D materials) to create "doping-free" transistors. These devices naturally possess low resistive contacts, meeting the stringent requirements of the International Roadmap for Devices and Systems (IRDS) for sub-decananometer technology.
these are also very very significant achievements but you dont see the media talking about it as much because these are lab results. IIsc is also growing wafer scale 2D chips. They are specifically partnering with L&T to do so using the national 2D material innovation lab. so what the chinese scientists have found is significant but its not that insane lmao.
IIsc has also submitted a proposal to develop armstrong scale chips which, "The proposal has been presented to the Principal Scientific Adviser (PSA) and the Ministry of Electronics and IT (MeitY). MeitY has shown strong positive interest, viewing it as a way for India to own the intellectual property (IP) for the next generation of chips rather than just manufacturing current ones."
500Cr is not a lot and meity has shown approval, probably why the 2D innovation lab was fast tracked.
We also have NoPo which is one of the few companies in the world which can eve make SWCNT and they also use the HiPCO process which is considered gold standard for electronics grade since they produce the smallest tubes with the best bandgaps etc. their HiPCO is 300% better in terms of iron residual which causes metallic tubes which is the main cause of defects, i.e they're 300% better than the original HiPCO process by rice university.
"NoPo reports a G/D ratio > 40, which is a benchmark for low structural defects. Their patented purification process removes 99% of catalyst particles, which is critical because residual metals (like iron) can cause short circuits in chips"
"NoPo is one of the few companies globally that offers Single Chiral SWCNTs (e.g., (6,5) and (7,5) chiralities). By providing a single chirality, they allow electronics manufacturers to control the bandgap of the semiconductor precisely—something bulk producers like OCSiAl don't typically prioritize."
ofc i used ai to find the data so here are sources Applications | NoPo Nanotechnologies.
Differences Between NoPo HiPCO and Rice HiPCO
The NoPo HiPCO technology has branched off from the Rice HiPCO. It uses new materials and newer techniques for mixing gases in order to improve the product and ensure stability.These advances and improvements in pursuit of the best possible Nanotubes has led to some marked differences between...
www.noponano.com
- Lowest Recorded Contact Resistance: Led by Prof. Mayank Shrivastava, a team at IISc invented a technique to engineer graphene contacts by studying the overlap of atomic orbitals between carbon and metal atoms. This allowed them to achieve the lowest recorded resistance for a 2D material-to-metal interface.
- MXene Transistors: More recently, IISc researchers used MXenes (a class of 2D materials) to create "doping-free" transistors. These devices naturally possess low resistive contacts, meeting the stringent requirements of the International Roadmap for Devices and Systems (IRDS) for sub-decananometer technology.
these are also very very significant achievements but you dont see the media talking about it as much because these are lab results. IIsc is also growing wafer scale 2D chips. They are specifically partnering with L&T to do so using the national 2D material innovation lab. so what the chinese scientists have found is significant but its not that insane lmao.
IIsc has also submitted a proposal to develop armstrong scale chips which, "The proposal has been presented to the Principal Scientific Adviser (PSA) and the Ministry of Electronics and IT (MeitY). MeitY has shown strong positive interest, viewing it as a way for India to own the intellectual property (IP) for the next generation of chips rather than just manufacturing current ones."
500Cr is not a lot and meity has shown approval, probably why the 2D innovation lab was fast tracked.
We also have NoPo which is one of the few companies in the world which can eve make SWCNT and they also use the HiPCO process which is considered gold standard for electronics grade since they produce the smallest tubes with the best bandgaps etc. their HiPCO is 300% better in terms of iron residual which causes metallic tubes which is the main cause of defects, i.e they're 300% better than the original HiPCO process by rice university.
"NoPo reports a G/D ratio > 40, which is a benchmark for low structural defects. Their patented purification process removes 99% of catalyst particles, which is critical because residual metals (like iron) can cause short circuits in chips"
"NoPo is one of the few companies globally that offers Single Chiral SWCNTs (e.g., (6,5) and (7,5) chiralities). By providing a single chirality, they allow electronics manufacturers to control the bandgap of the semiconductor precisely—something bulk producers like OCSiAl don't typically prioritize."
ofc i used ai to find the data so here are sources Applications | NoPo Nanotechnologies.
Differences Between NoPo HiPCO and Rice HiPCO
The NoPo HiPCO technology has branched off from the Rice HiPCO. It uses new materials and newer techniques for mixing gases in order to improve the product and ensure stability.These advances and improvements in pursuit of the best possible Nanotubes has led to some marked differences between...
Technology Development Board
The pro-active role of TDB is in all the above categories in order that the beneficial effects can accrue to the economy and society as a whole, in a sustainable manner..
tdb.gov.in
NoPo Nanotechnologies: Bengaluru startup that makes silicon replacement for chips to scale production - The Economic Times
Single-walled carbon nanotubes (SWCNTs), which Bengaluru-based NoPo makes, have applications of a wide range, from EV battery manufacturing, where the material can improve energy density, to design of semiconductors.
"targeted project to integrate NoPo’s HiPCO nanotubes into Sodium-ion batteries, which India views as a strategic alternative to Lithium."
LTSCT & IISc Ink Strategic MoU to Establish India’s First National 2D Innovation Hub
Mumbai, September 03, 2025: Today at Day 2 of Semicon India 2025, L&T Semiconductor Technologies (LTSCT) and the Indian Institute of Science (IISc), Bangalore, signed a strategic Memorandum of Understanding (MoU) to collaborate on the development of a national 2D Innovation Hub.
they want to demonstrate a simple microprocessor level prototype by 2027 and then scale quickly to specialized space based stuff by 2029-2030 and then eventually commercial stuff along with the rest of the world. So we wont be far behind if at all behind in this compared to the rest of the world.
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Also btw the first integration of CNT will be to replace the copper wires on the semiconductors, this is the current active area,
pmc.ncbi.nlm.nih.gov
Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects - PMC
Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads ...
pmc.ncbi.nlm.nih.gov
Of course not. This breakthrough was on wafer production, not fabrication. But you can't really make transistors without mass produced ultrapure wafers, can you? This is essentially the first step in that direction. MoS2 didn't have anything like Silicon's Czokrowski method before. There's a lot to be done to translate lab results to industrial production.
From what little reading I have done on the subject, Molybdenum Disulphide is seen as the most promising 2d material candidate to replace silicon in logic chips.
MoS2 is the most viable alternative to silicon, so it naturally gets the lion's share of investment and headlines.
Source? I went through the links you posted and unless I missed something, all of them talked about growing wafer scale 2D material in the future.
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Electrically Controlled High Sensitivity Strain Modulation in MoS2 Field-Effect Transistors via a Piezoelectric Thin Film on Silicon Substrates - PMC
Strain can modulate bandgap and carrier mobilities in two-dimensional (2D) materials. Conventional strain-application methodologies relying on flexible/patterned/nanoindented substrates are limited by low thermal tolerance, poor tunability, and/or ...
pmc.ncbi.nlm.nih.gov
There is significant Indian research going on for it as well.
"Source? I went through the links you posted and unless I missed something, all of them talked about growing wafer scale 2D material in the future."
ah yes mb the thing was singed in sep 2025 so the cleanroom construction and other installations are happening rn. Youd probably see the actual chips in 2027 or late 2026.
as for current research :
Division of EECS, IISc Bangalore
IISc is the premier institute for advanced scientific and technological research and education in India.
eecs.iisc.ac.in
Division of EECS, IISc Bangalore
IISc is the premier institute for advanced scientific and technological research and education in India.
eecs.iisc.ac.in
"P-type MoS2 : They have successfully demonstrated p-channel conduction in MoS2, which is the "holy grail" for creating CMOS (Complementary Metal-Oxide-Semiconductor) circuits that consume very little power."
all this happens at this lab:
CeNSE | Centre for Nano Science and Engineering (CeNSE)
www.cense.iisc.ac.in
one of the profs got named an IEEE fellow, you don't get that for non significant research.
The chinese are ahead right now but that is expected, this is still a developing technology so there is relatively plenty of time to still catch up(especially with the gov finally realising the importance research) or at least be 1-3 years behind which is not bad at all.
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